Integrated circuits (ICs) are often represented by models that represent their netlist connectivity or functional behavior. For hierarchically designed integrated circuits, a model is made up of a hierarchy of circuit blocks. When a tool, such as a circuit analysis tool, is used to carry out an action (e.g. circuit analysis, simulation or design tools) on the circuit model, the entire model is generally used in the action. With large and complex integrated circuits, this means that the analysis or other action carried out by the tool operates on an extremely large body of data. This can be the case, even when there is only a small portion of the circuit that is relevant to the particular action of the tool. This can result in the need for enormous amounts of computing time and memory to carry out a given analysis (on the order of days of computing time is not an unreasonable estimate in some cases).